- Title
- Algorithms and hardware implementation of a processor for low complexity and high performance multi-antenna receivers
- Creator
- Murray, Alan T.
- Relation
- University of Newcastle Research Higher Degree Thesis
- Resource Type
- thesis
- Date
- 2012
- Description
- Research Doctorate - Doctor of Philosophy (PhD)
- Description
- Many high-speed wireless communication systems employ multiple antennas at both transmitter and receiver to achieve increased throughput or reliability without requiring either additional bandwidth or increased transmit power. A key challenge, however, is the accurate decoding of transmitted information in a computationally efficient manner. While a large number of approaches to multiple-input multiple-output (MIMO) detection have appeared in the literature, comparatively few high-performance algorithms have been developed through to a hardware implementation suitable for use in low-power mobile devices. One popular approach to MIMO detection in recent years draws on the mathematical theory of lattices and lattice-reduction to design pre-processors for low-complexity conventional receivers based on zero forcing (ZF) or minimum mean square error (MMSE) detection. In the literature, few known examples of lattice-reduction aided detection (LRAD) and no known hardware implementations exist which are capable of generating the soft (probabilistic) information needed for coded MIMO communications. This thesis presents a novel full diversity, subspace basis and lattice-reduction aided soft-output MIMO detection strategy, which we term absolute bit cover detection (ABCD). ABCD is shown to have computational complexity that increases only linearly as the total number of bits transmitted increases, whilst producing bit reliability information for improved error detection and correction performance. The developed unified hardware architecture represents the first known implementation of a full-diversity, subspace basis and lattice-reduction aided soft-output MIMO digital signal processor. The unified nature of this architecture allows implementations to be scaled to meet the requirements of the future generation wireless standards of the 3GPP and IEEE. This thesis includes an implementation targeting 3GPP R8 LTE which is capable of a throughput of 300Mbit/s when operating in a (nT, nR) = (4, 4) 64-QAM system, whilst being appropriate for use in mobile environments where relative receiver motion is a particular challenge.
- Subject
- multiple-input multiple-output; VLSI; ASIC; lattice reduction; symbol detection
- Identifier
- http://hdl.handle.net/1959.13/1036980
- Identifier
- uon:13388
- Rights
- Copyright 2012 Alan T. Murray
- Language
- eng
- Full Text
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